HW Acceleration with High-Level Synthesis

Embedded systems continue to see increasing demands for compute capability. Processor speeds however are not increasing sufficiently to meet these demands. One approach is to move functions from software running on general purpose CPU into bespoke hardware accelerators. Hardware accelerators have much greater parallelism and reduce data movement, enabling them to dramatically exceed the performance and efficiency of software. This session will introduce High-Level Synthesis, a technology that allows a developer to take a C++ function and automatically compile it into an RTL hardware description, suitable to be deployed into an ASIC or FPGA.