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High-Level Synthesis Verification Technologies and Techniques

視聴時間の目安: 17 分

When designing with High-Level Synthesis (HLS) many have questions regarding verification. Waiting to verify until you have post-HLS RTL is too late and too inefficient. This session will describe applying known and trusted static, formal and dynamic approaches to verification performed at the C++ or SystemC HLS level of abstraction.

講演者の紹介

Siemens EDA

David Aerne

Verification Technologist

Dave Aerne is a Verification Technologist within the Calypto Systems Division, focusing on HLV (High-Level Verification) solutions. His particular areas of expertise are the UVM and Verification IP. Prior to joining the EDA industry, he gained over 18 years of SoC Design and Verification experience in various roles at semiconductor companies and fabless startups. Dave received a BSCompE from the University of Illinois at Urbana-Champaign and a MSCompE from National Technological University in Fort Collins, Colorado.

High-Level Synthesis Verification Technologies and Techniques

共有

講演者の紹介

David Aerne

関連情報

High-Level Synthesis Verification Technologies and Techniques

共有

講演者の紹介

David Aerne

関連情報

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