HW Acceleration with High-Level Synthesis
Embedded systems continue to see increasing demands for compute capability. Processor speeds however are not increasing sufficiently to meet these demands. One approach is to move functions from software running on general purpose CPU into bespoke hardware accelerators. Hardware accelerators have much greater parallelism and reduce data movement, enabling them to dramatically exceed the performance and efficiency of software. This session will introduce High-Level Synthesis, a technology that allows a developer to take a C++ function and automatically compile it into an RTL hardware description, suitable to be deployed into an ASIC or FPGA.
Meet the speaker
Richard Langridge
AE Manager
Richard Langridge works for Siemens EDA as an Application Engineering Manager. Richard has more than 30 years of experience in EDA and design, ranging from RTL Synthesis and Low-Power to High-Level Synthesis (HLS) and Formal Methods. Richard manages Low-Power engagements in a variety of Semiconductor customers.
Related resources
SLEC System Factsheet
SLEC System is a good fit for design teams verifying their RTL implementation by formally comparing it against functional SystemC/C++ models
Catapult High-Level Synthesis and Verification Fact Sheet
Industry leading C++/SystemC High-Level Synthesis with Low-Power estimation/optimization. Design checking, code and functional coverage verification plus formal make HLS more than mere “C to RTL.
StreamTV’s SeeCubic: Catapult HLS enables Ultra-D 3D without glasses
StreamTV's SeeCubic faced an impossible task: develop a real-time conversion IP block for a custom SoC without knowing the target technology. This IP was critical for their glasses-free 3D solution.