Enabling IC Functional Verification Across Applications

OVERVIEW

As the SoCs and IC designs are getting more complex, delivering smarter and reliable systems is growing into a hard and challenging task. From complete digital verification of IP/SoC to verification of precision systems that require SPICE circuit simulator has become quite challenging.

While design & verification is a high-effort task, and debugging is slow, many times just simulation cannot hit all pipeline corner-cases. At the same time, writing functional coverage models is difficult and we face functional/structural coverage closure issues.

On similar lines, denser and smaller ICs introduce added complexity for analog design and verification. Worsening device noise and increasing post-layout parasitic can significantly impact precision, hence requiring more complex design and verification techniques to compensate for process induced effects. This is especially the case for critical components dealing with high frequency data transport such as SerDes high speed links that are communication conduits within, between and outside chips. Similarly, data converters are critical IPs that convert digital to analog signals and vice-versa and are responsible for connecting the digital world to the analog world. Concurrently, fast simulations are required to achieve timely tape-outs.

To address above challenges in Analog & Digital domains, a comprehensive verification solution is available through our Siemens IC Verification Platform.

WHAT YOU WILL LEARN

• How to speed-up Analog & Digital verification and increase quality of code.
• Digital design & verification solutions - including formal verification approaches - what they are, how to apply them, which can be utilized by any engineer who wants to speed-up verification by >10x and increase quality of code.
• Analog verification solutions - Analog FastSPICE Platform along with Mixed Signal Capabilities on advance debug with Symphony platform to address today’s analog verification challenges

WHO SHOULD ATTEND

• Design Engineer and Verification Engineers in Analog & Digital domain
• CAD Engineers
• Engineering Managers, Project Managers and Architects

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MEET THE SPEAKERS

Kapil Kumar
Application Consultant, Functional Verification
Siemens EDA

Kapil is an experienced professional with a demonstrated history of working in the Semiconductor Industry and Academics for over a decade.

He has a strong background in deploying EDA flows and methodologies, developing Verification flows using SystemVerilog, Universal Verification Methodology (UVM) for SOC/IP Verification & simulation-performance, using Questa Portfolio.

He is also a professional trainer for SystemVerilog and UVM and his working domains include technical solutions, consulting practices and business development at Siemens EDA.

Kapil is an MTech in Microelectronics and Embedded Systems Technology and has published various research papers.

Gaurav Kumar
Senior Application Engineer
Siemens EDA

Gaurav is a Senior Application Engineer for AMS Suite of Products at Siemens EDA, handling AFS, Symphony, Eldo, QADMS and Solido family of products.

He has more than a decade of industry experience, working as Application and CAD Engineer for various industry leading Custom IC Design and Simulation solutions. He holds B. Tech in Electronics and Communication Engineering and M.Tech in Microelectronics.

Keshav Joshi
Application Engineer Manager
Siemens EDA

Keshav is an Application Engineering Manager with Scalable Verification Solutions Division at Siemens EDA. He carries about 20 years of industry experience in design and verification field.

He is with Siemens for last 15 years and has worked on low power verification, functional simulation, and formal technologies. Currently he is leading and Application Engineering team catering to Emulation and Prototyping customers.