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Moving Between FPGA and ASIC with High-Level Synthesis

Moving Between FPGA and ASIC with High-Level Synthesis

Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Siemen’s Catapult team about how to use HLS to accelerate your design flow.

相關資訊

針對不同的 FPGA 平台最佳化 HLS 程式碼
White Paper

針對不同的 FPGA 平台最佳化 HLS 程式碼

在此白皮書中，我們將審視一個簡易的卷積濾波器，並概述如何使用 HLS 將它導入至不同的 FPGA 平台。我們還將著重於導入不同平台時為獲得最佳效能可能需要的不同最佳化，以及可用來獲得更佳效能的編碼形式。

Rapid Algorithm to HW: Using HLS for Computer Vision and Deep Learning Seminar
Webinar

Rapid Algorithm to HW: Using HLS for Computer Vision and Deep Learning Seminar

How HLS helps project teams rapidly & accurately explore power/performance of algorithms, quickly get to FPGA implementations to create demonstrator/prototypes & use same source RTL IP for ASIC implementation.