This presentation introduces Harvard's experiences of using Catapult HLS in research projects. Since 2018, we have taped out several chips with hardware components designed in SystemC. The HLS design flow has been very helpful to shorten development cycle of accelerators as well as providing a way to quickly prototype different research ideas. First half of the talk focuses on our learnings with the HLS tool. Even though comparing with Verilog RTL, SystemC allows us to design hardware in a more concise and efficient manner, we find it difficult at first to figure out what kind of coding is more appropriate. Specifically, how to pass HLS and achieve pipeline initial interval “II = 1” for critical parts of accelerator designs. Throughout many trial and errors, we have developed intuitions and strategies for SystemC coding. In addition, we also extensively leverage standard hardware IPs provided in Mentor Algorithmic C and NVIDIA MatchLib to implement our designs. For the second half, we share some projects involving Catapult HLS. One of them is about proposing adaptive floating-point (FP) quantization to replace integer (INT) quantization for NNs, especially for large-scale NLP models. For hardware evaluation of this idea, we utilize Catapult HLS and PowerPro to compare power and area of FP and INT MAC datapath designs. The work has been selected as the best research paper in DAC 2020 conference.