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Telechips: RTL Hardware Design Acceleration for On-The-Fly Image (De-)Warper in Automotive SoC Using C++ HLS

Telechips designed a new dewarping engine processing video stream data on-the-fly, which differs from the traditional GPU-based memory-to-memory approach, by utilizing hierarchical design methodology in Catapult HLS.

Dewarping (i.e., fisheye lens distortion correction) plays an important role in automotive image processing as fisheye cameras are widely used in automotive applications. We designed a new dewarping engine processing video stream data on-the-fly, which differs from the traditional GPU-based memory-to-memory approach, by utilizing hierarchical design methodology in Catapult HLS. We designed and verified the entire IP including line memory, position calculator, pixel interpolator, and BUS interface (AXI4) in C++. Meanwhile, HDL was only used for describing the register bank and RTL wrapper for the IP. We started designing from architecture search in a top-down manner and created C++ classes for each module we needed. Then we designed each module bottom-up, constructing a hierarchy of classes. Finally, we compared the result of our Catapult C++ design to that of reference Python code which performs fisheye dewarping using an OpenCV library. To verify the final RTL, we used our noble verification environment, TcSimGen, and compared the output images from C++ and RTL test benches to check if they match. Thanks to C++ simulation which runs much faster than RTL simulation (~100x), it took a total of 9 months to design and verify the million-gate dewarping IP by one hardware engineer. Furthermore, it was verified post-silicon in Dolphin 5, our automotive AP, and N-Dolphin, our AI accelerator.

主讲嘉宾

Telechips

Sangwan Kim

Team Leader of SoC Development Platform

Sangwan Kim is team leader of SoC Development Platform at Telechips.
As a Verification Engineer, he leads the SoC platform design team, especially for ARMV7 and ARMV8 CPU, GIC, SMMU, and PCIE verification.
He manages the development of Telechips' CAD tool automation and verification platform automation.

He is also in charge of verification environment integration management and development for regression and automation.

He has developed an IP-XACT-based scripting automation design environment. He also has experience in developing super resolution IP using HLS.
He holds a bachelor's and master's degree in electrical engineering.

Telechips

Dooyoung Go

Design Engineer

Dooyoung Go is design engineer in the SoC IP Design Team at Telechips.
He is working on image processing, NPU related, AXI interface, Vehicle Chip Processor/MCU design.

In graduate school, he conducted research on digital signal processing, computer vision, and medical ultrasound image processing in the fields of SW development and HW development.

He holds a bachelor's and master's degree in electronics engineering from Sogang University.

Siemens EDA

William Lee

Consultant Application Engineer

William Lee is consultant application engineer at Siemens EDA.
He is supporting Catapult HLS, which is a fast and effective RTL implementation of functions described in high level languages such as C/C++/SystemC.

He is particularly interested in HLS implementation of applications in the fields of video image processing and AI/ML.

He has also worked as an RTL design and verification support engineer, delivering QuestaSim digital logic simulator technical support and debugging, coverage closure, formal verification, and SV/UVM.

Before joining Siemens EDA in 2015, he had 6 years of experience in IP development and Soc mass production in various processes as an ASIC/SoC RTL design and verification engineer, including camera image signal processing, memory controller design, memory optimization, and low power design.

He holds a B.S and Ph.D.(ABD) degree from Hanyang University, electronics and electrical Engineering.

Telechips: RTL Hardware Design Acceleration for On-The-Fly Image (De-)Warper in Automotive SoC Using C++ HLS

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