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STMicroelectronics: A Common C++ and UVM Verification Flow of High-Level IP

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STMicroelectronics presents a unified way to integrate the definition of RTL and C functional coverage and assertion (reducing the coding effort) as well as a method to add constraints to the random values generated in UVMF.

High-Level Synthesis has the great advantage of keeping the design at an algorithmic level, simplifying the translation into RTL. High-Level Verification at C++ level can help to catch several bugs in the earliest stage of the design. The usage of the UVMF (UVM Framework), generated by Catapult, is a good starting point to complete the verification at RTL Level. STMicroelectronics presents a unified way to integrate the definition of RTL and C functional coverage and assertion (reducing the coding effort) as well as a method to add constraints to the random values generated in UVMF.

主讲嘉宾

Politecnico di Torino

Stefano Moncalvo

MSc Electronic Engineering student

MSc Electronic Engineering student at Politecnico di Torino, specializing in embedded systems. Currently working on the master’s thesis, developing a verification flow for High-Level Synthesis IPs in collaboration with STMicroelectronics.

STMicroelectronics

Martino Zerbini

Digital Design Engineer

Martino Zerbini joined STMicroelectronics in 2006 as Digital Design Engineer. He started using CatapultC in 2010 and introduced its usage inside the Audio Division design team. The main activity was the development of DSP part of Class-D amplifiers. Later he moved inside the MEMS Actuator Division developing laser and micro-mirror drivers. Since 2019, Martino focused his interests on Digital Verification, he is responsible for developing and executing an integrated strategy for the chip verification. From 2021 this includes IPs developed with CatapultC.