点播式网络研讨会
Moving Between FPGA and ASIC with High-Level Synthesis
Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Siemen’s Catapult team about how to use HLS to accelerate your design flow.
相关资源
Webinar
Simulation process and data management for ship design
Learn how to create a seamless ship design workflow with simulation and data sharing. Ensure effective collaboration and provide the right information.
Webinar
释放集成式 CAE 工作流程的强大功能，实现快艇的高效设计
了解如何使用系统仿真创建推进系统，并将其部署在计算流体动力学（CFD）自推进系统仿真中，以评估最大速度。
White Paper
如何通过仿真工具推动船舶设计流程
摆脱低效的船舶设计螺旋循环。本白皮书将阐述使用西门子解决方案的仿真驱动型船舶设计流程。阅读如何充分利用当今可用的数字化技术。