Early AXI4 SOC Performance Verification Using NVIDIA MatchLib and Catapult HLS

NVIDIA Matchlib is a new open source library that enables much faster design and verification of SOCs using High-Level Synthesis (HLS). One of the primary objectives of Matchlib is to enable performance accurate modeling of SOCs in SystemC/C++. With these models, designers can identify and resolve issues such as bus and memory contention, arbitration strategies, and optimal AXI4 interconnect structure at a much higher level of abstraction than RTL. In addition, much of the system level verification of the SOC can occur in SystemC/C++, before RTL is even created. Once the architectural performance is verified, this flow provides a fully automated flow to silicon using Catapult HLS. This webinar will introduce NVIDIA Matchlib and its usage with Catapult HLS using some AXI4 SOC demonstration examples.

What you will learn:

• Introduction to NVIDIA MatchLib
• What is motivating a change in design and verification flow
  complexity
• How risk/complexity in many of today’s SOCs differs from the past
• How to write HLS models using NVIDIA MatchLib
• How Matchlib significantly improves simulation speed and
  verification efficiency
• Where to find more information and examples for MatchLib from
  Siemens EDA and NVIDIA

Who should view:

• RTL designers, hardware architects, and managers interested in
  moving up to HLS