High-Level Synthesis (HLS) extends the traditional design flow, providing a new and powerful approach to hardware design. It is important to understand the fundamentals of HLS and how HLS bridges the gap between the RTL designer and architect, and functional verification and RTL verification. This web seminar will provide an introduction to HLS and how an abstract, untimed algorithm representation is prepared for HLS, then transformed and optimized for power, performance and area by Catapult, resulting in high-quality RTL. Additionally, this seminar will introduce changes to the verification methodology that complement an HLS flow.

What you will learn:

• The HLS Design Flow compared to the traditional design flow
• What does the use of HLS provide?
• The fundamentals of HLS:
• Modeling for HLS
• HLS transformations / optimizations
• HLS technology mapping
• HLS scheduling
• HLS Analysis
• HLS Verification
• HLS is proven technology

Who should attend:

• RTL designers, hardware architects, and managers interested in
  moving up to HLS