webinar na żądanie
Moving Between FPGA and ASIC with High-Level Synthesis
Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Siemen’s Catapult team about how to use HLS to accelerate your design flow.
Powiązane treści
Webinar
Porting Vivado HLS Designs to Catapult HLS Platform
This webinar will cover how to port an existing HLS design developed within the Xilinx® Vivado® HLS environment into Siemens' Catapult® HLS Platform.
Webinar
Edge Detection Walkthrough Video Series
9-part series provides a step-by-step walkthrough of what's needed to take a C++ floating-point algorithm all the way to optimized RTL using Catapult.