온디맨드 웨비나

Moving Between FPGA and ASIC with High-Level Synthesis

공유

Moving Between FPGA and ASIC with High-Level Synthesis

Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Siemen’s Catapult team about how to use HLS to accelerate your design flow.

관련 자료

서로 다른 FPGA 플랫폼의 HLS 코드 최적화
White Paper

서로 다른 FPGA 플랫폼의 HLS 코드 최적화

본 백서에서는 간단한 컨볼루션 필터를 살펴보고 상위수준합성(HLS)을 사용하여 다른 FPGA 플랫폼에 적용하는 방법을 간략하게 설명합니다.

Rapid Algorithm to HW: Using HLS for Computer Vision and Deep Learning Seminar
Webinar

Rapid Algorithm to HW: Using HLS for Computer Vision and Deep Learning Seminar

How HLS helps project teams rapidly & accurately explore power/performance of algorithms, quickly get to FPGA implementations to create demonstrator/prototypes & use same source RTL IP for ASIC implementation.