Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL / GDS) RTL lint / formal check tools cannot be run on HLS RTL (as the errors cannot be correlated to HLS source code) Onespin systemC/C++ extension DV help to overcome this challenge. This session will be presented by Siemens on behalf of Infineon Technologies AG.
발표자 소개
Vlada Kalinic
SystemC Product Specialist
Vlada Kalinic is the SystemC Product Specialist at Siemens EDA, and is involved in the evaluations with the new customers as well supporting the current portfolio of the customers to improve the current SystemC flows. Vlada has also another role, as Product Specialist of EC-FPGA in OneSpin. Vlada holds a master’s degree with honors in Electrical and Computer Engineering, Embedded Systems and Algorithms from the University of Novi Sad (Serbia). Prior to Mentor/Siemens, Vlada worked with OneSpin for 5+ years and was involved in various successful evaluations with SystemC and EC-FPGA customers.
관련 자료
식음료 산업의 제품 및 프로세스 시뮬레이션
기업이 식음료에 제품 및 프로세스 시뮬레이션을 수행하여 더 많은 제품을 시장에 빠르게 출시할 수 있는 초석을 마련하는 방법을 알아보십시오.
제품 소음을 줄이는 가장 효과적인 3가지 소음 제어 방법
본 백서에서 제품 소음을 줄이는 가장 효과적인 3가지 소음 제어 방법을 알아보십시오.