High-Level Synthesis Verification Technologies and Techniques
When designing with High-Level Synthesis (HLS) many have questions regarding verification. Waiting to verify until you have post-HLS RTL is too late and too inefficient. This session will describe applying known and trusted static, formal and dynamic approaches to verification performed at the C++ or SystemC HLS level of abstraction.
발표자 소개
David Aerne
Verification Technologist
Dave Aerne is a Verification Technologist within the Calypto Systems Division, focusing on HLV (High-Level Verification) solutions. His particular areas of expertise are the UVM and Verification IP. Prior to joining the EDA industry, he gained over 18 years of SoC Design and Verification experience in various roles at semiconductor companies and fabless startups. Dave received a BSCompE from the University of Illinois at Urbana-Champaign and a MSCompE from National Technological University in Fort Collins, Colorado.
관련 자료
효율적인 ECAD-MCAD 공동 설계로 한 번에 설계 성공 달성
본 문서에서는 효율적인 ECAD-MCAD 공동 설계를 통해 설계 팀이 신제품 개발 과정에서 많은 비용을 초래하는 전자기계 문제를 해소하고 한 번에 성공할 가능성을 높이는 방법에 대해 설명합니다.
Leveraging ECAD-MCAD Data in Simulation-Driven Design of Smart Products
ECAD MCAD collaboration, Thermal Simulation, Smart product design, Power management, physical design of electronic products