Low Power Considerations for Verification

The verification state space can grow exponentially as a function of the number of power domains in a system. UPF power states can help bound the verification state space and enable tool automation.

Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. We will discuss how to use these commands to manage verification.

What you will learn:

• The verification challenges associated with low power designs
• How the UPF power states constraint verification
• How UPF power states enable verification automation

Who should attend:

• Design & Verification Engineers & Managers designing power managed
  ICs