Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL / GDS) RTL lint / formal check tools cannot be run on HLS RTL (as the errors cannot be correlated to HLS source code) Onespin systemC/C++ extension DV help to overcome this challenge. This session will be presented by Siemens on behalf of Infineon Technologies AG.
講演者の紹介
Vlada Kalinic
SystemC Product Specialist
Vlada Kalinic is the SystemC Product Specialist at Siemens EDA, and is involved in the evaluations with the new customers as well supporting the current portfolio of the customers to improve the current SystemC flows. Vlada has also another role, as Product Specialist of EC-FPGA in OneSpin. Vlada holds a master’s degree with honors in Electrical and Computer Engineering, Embedded Systems and Algorithms from the University of Novi Sad (Serbia). Prior to Mentor/Siemens, Vlada worked with OneSpin for 5+ years and was involved in various successful evaluations with SystemC and EC-FPGA customers.
関連情報
PLMとは何か。なぜクラウド型PLMなのか。
PLMとは何かコスト効果が高く高速のクラウド型Teamcenter Xを導入すると、革新的な製品を市場にいち早く投入できます。その詳細をご覧ください。詳細情報
CAD設計者の時間を奪っている最大の要因とは?
CADに弱点がある? CAD設計には無駄にしている時間があります!