Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL / GDS) RTL lint / formal check tools cannot be run on HLS RTL (as the errors cannot be correlated to HLS source code) Onespin systemC/C++ extension DV help to overcome this challenge. This session will be presented by Siemens on behalf of Infineon Technologies AG.
講演者の紹介
Vlada Kalinic
SystemC Product Specialist
Vlada Kalinic is the SystemC Product Specialist at Siemens EDA, and is involved in the evaluations with the new customers as well supporting the current portfolio of the customers to improve the current SystemC flows. Vlada has also another role, as Product Specialist of EC-FPGA in OneSpin. Vlada holds a master’s degree with honors in Electrical and Computer Engineering, Embedded Systems and Algorithms from the University of Novi Sad (Serbia). Prior to Mentor/Siemens, Vlada worked with OneSpin for 5+ years and was involved in various successful evaluations with SystemC and EC-FPGA customers.
関連情報
消費者を中心に据えたコンシューマー製品 (CPG) イノベーションを加速
シーメンスとアクセンチュアが、CPG業界の変革への適応をサポートします。消費者を中心に据えた戦略、オムニチャネルの動向、スマート・パッケージングに関する知識を高め、市場をリードしましょう。
コンシューマー製品の市場投入を3倍早める
毎朝の挽きたてのコーヒーの香りと味に勝るものはあるでしょうか。ほとんどの消費者にとってはそうではなくても、コンシューマー製品メーカーにとっては製品の市場投入期間を3倍早められたら非常にそそられるでしょう。
CPG業界に変革をもたらす、シーメンスとアクセンチュアの革新的なソリューション
シーメンスとアクセンチュアの革新的なクラウドベースのソリューションが、CPG製品開発にどのように変革をもたらすかを紹介します。