HW Acceleration with High-Level Synthesis
Embedded systems continue to see increasing demands for compute capability. Processor speeds however are not increasing sufficiently to meet these demands. One approach is to move functions from software running on general purpose CPU into bespoke hardware accelerators. Hardware accelerators have much greater parallelism and reduce data movement, enabling them to dramatically exceed the performance and efficiency of software. This session will introduce High-Level Synthesis, a technology that allows a developer to take a C++ function and automatically compile it into an RTL hardware description, suitable to be deployed into an ASIC or FPGA.
講演者の紹介
Richard Langridge
AE Manager
Richard Langridge works for Siemens EDA as an Application Engineering Manager. Richard has more than 30 years of experience in EDA and design, ranging from RTL Synthesis and Low-Power to High-Level Synthesis (HLS) and Formal Methods. Richard manages Low-Power engagements in a variety of Semiconductor customers.
関連情報
ビデオ: 消費財 (CPG) 向けEnterprise Recipe Management - レシピ開発プロセスを効率化
シーメンスのEnterprise Recipe Managementで素早くレシピを変貌させ、スケールアップさせましょう。生産を合理化し、試用時間を短縮します。こちらのビデオをご覧になると、レシピ開発プロセスに革命を起こす方法が分かります。
レシピ管理ソフトウェアとデジタル・トランスフォーメーションでCPGのイノベーションを推進
レシピ管理ソフトウェアは、R&Dの可能性を高め、複雑な新製品の開発を可能にします。詳細情報
CPG製造における調製品開発の最適化
このウェビナーでは、調製品開発を最適化してCPG製造のイノベーションを効率化する方法を学びます。