From HLS Component to a Working Design

Complex algorithms do not exist in a vacuum. After High-Level Synthesis (HLS) is used to create an RTL component, to be useful, it needs to be integrated into a larger system. This means connecting it to other components, a processor, and even software. Once integrated, the system needs to be verified. The verification of the complete environment does not just mean functional correctness, but also needs to consider performance, and in some cases power. This webinar details approaches to integrating accelerator blocks into processor-based sub-systems, interfacing to software, and verifying the accelerator in the context of the larger system. It also covers deploying the system onto a FPGA prototyping board.

This webinar is part 4 of the webinar series HLS for Vision and Deep Learning Hardware Accelerators.

What you will learn:

• How HLS is used to implement a computer vision algorithm in either
  an FPGA or ASIC technology and the trade-offs for power and
  performance.
• How HLS is employed to analyze unique architectures for a very
  energy-efficient inference solution such as a CNN (Convolutional
  Neural Network) from a pre-trained network.
• How to integrate the design created in HLS into a larger system,
  including peripherals, processor, and software.
• How to verify the design in the context of the larger system and how
  to deploy it into an FPGA prototype board.