NVIDIA: Design and Verification of a Machine Learning Accelerator SoC Using an Object-Oriented HLS-Based Design Flow
Using an Object-Oriented HLS-Based Design Flow
A high-productivity digital VLSI flow for designing complex SoCs is presented in this webinar. It includes High-Level Synthesis tools, an efficient implementation of Latency-Insensitive Channels, and MatchLib - an object-oriented library of synthesizable SystemC and C++ components. The flow was demonstrated on a programmable machine learning inference accelerator SoC designed in 16nm FinFET technology.
NVIDIA’s DAC Paper: A Modular Digital VLSI Flow for High-Productivity SoC Design.
What you will learn:
- How to shorten development time & cost
- A high-productivity digital VLSI flow for designing complex SoCs
- Efficient implementation of Latency-Insensitive Channels
- MatchLib - an object-oriented library of synthesizable SystemC and
C++ components
Who Should Attend
- RTL designers
- ASIC Designers
- Engineers
- Hardware architects
- Managers
Relatore
Brucek Khailany
Senior Director of ASIC and VLSI Research
Brucek Khailany joined NVIDIA in 2009 and currently leads the ASIC & VLSI Research group. During his time at NVIDIA, he has contributed to projects within research and product groups on topics spanning computer architecture, unit micro-architecture, and ASIC and VLSI design techniques. Dr. Khailany is also currently the Principal Investigator to a NVIDIA-led team under the DARPA CRAFT project researching high-productivity design methodology and design tools. Previously, Dr. Khailany was a Co-Founder and Principal Architect at Stream Processors, Inc. (SPI) where he led research and development activities related to highly-parallel programmable processor architectures. He received his Ph.D. and Masters in Electrical Engineering from Stanford University and received B.S.E. degrees in Electrical Engineering and Computer Engineering from the University of Michigan.
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