INOVA Semiconductors and Coseda: Paradigm Shift in Mixed Signal ASIC Design, Adopting SystemC and High-Level-Synthesis vs. Traditional RTL Design Flow
The authors present the adoption of SystemC for High-Level-Synthesis replacing the traditional RTL design flow. A steady increase in the need for connectivity in the automotive industry and the resulting higher complexity in the individual ASICs requires a novel methodology within the ASIC design phase. This is now being implemented using a new design flow starting from an abstract network simulation in SystemC down to either FPGA-Prototyping (simulating a complex network topology) or the tapeout RTL for an individual ASIC. In conclusion, the authors will present the ease of use and the value-add of the HLS methodology in an automotive context.
Relatori
Fabian Kluge
Systems Engineering Manager
Fabian Kluge is a Systems Engineering Manager at INOVA Semiconductors, working on architectures and concepts for new automotive serializers and networking products, now adopting SystemC as a modelling language. He has a strong background in FPGA and general electronics development including various high-speed interfaces. He received his master’s degree in electrical engineering from Technical University Munich in 2017, specializing in EDA and radar technologies.
Thomas Arnt
Application Engineering Manager
Thomas Arndt is an Application Manager at COSEDA Technologies, focusing on system level design and simulation solutions. He has over 20 years of experience in the chip design and the EDA industry. His particular areas of expertise are in the field of digital as well as analog system design, simulation and High-Level Synthesis. Prior to joining COSEDA, he was working at the Fraunhofer Institute for Integrated Circuits, one of the largest research institutions in the field of design automation in Europe. He received his diploma in electrical engineering from the Technical University of Dresden.
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