HLS 101 - What Every RTL HW Design Team Needs to Know
High-Level Synthesis (HLS) extends the traditional design flow, providing a new and powerful approach to hardware design. It is important to understand the fundamentals of HLS and how HLS bridges the gap between the RTL designer and architect, and functional verification and RTL verification. This webinar will provide an introduction to HLS and how an abstract, untimed algorithm representation is prepared for HLS, then transformed and optimized for power, performance and area by Catapult, resulting in high-quality RTL. Additionally, this webinar will introduce changes to the verification methodology that complement an HLS flow.
What you will learn:
- The HLS Design Flow compared to the traditional design flow
- What does the use of HLS provide?
- The fundamentals of HLS:
- Modeling for HLS
- HLS transformations / optimizations
- HLS technology mapping
- HLS scheduling
- HLS Analysis
- HLS Verification
- HLS is proven technology
Relatore
Stuart Clubb
Technical Product Management Director
Stuart is responsible for Catapult HLS Synthesis and Verification Solutions since July 2017. Prior to this role, Stuart had been successfully managing the North American FAE team for Mentor/Siemens and Calypto Design Systems and was key to the growth achieved for the CSD products after the Calypto acquisition. Moving from the UK in 2001 to work at Mentor Graphics, Stuart held the position of Technical Marketing Engineer, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University, London, with a Bachelors of Science.
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