Stanford/AMD: Automated Methodology for Efficient Hardware Accelerator
Mobile devices today are composed of many specialized accelerators to achieve high-performance and low-power specifications. However, accelerator design and validation time is a limiting factor in creating these accelerator-rich SoCs. We address this problem by demonstrating the effectiveness of using new programming languages and existing hardware synthesis tools to drastically decrease the time needed to explore the design space of hardware accelerators. By pairing the image-processing language Halide with the Catapult® High-Level Synthesis tool, different accelerator designs can be rapidly produced and evaluated for performance, area, and power.
In this webinar, Jeff Setter demonstrates the effectiveness of using new programming languages and existing hardware synthesis tools to drastically decrease the time needed to explore the design space of hardware accelerators.
What you will learn:
- Effectiveness of using new programming languages and existing
hardware synthesis tools to drastically decrease the time needed to
explore the design space of hardware accelerators - How accelerator designs can be rapidly produced and evaluated for
performance, area, and power - Benefits of pairing the image-processing language Halide with the
Catapult® High-Level Synthesis tool
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