Ultra-D technology provides a solution for glasses-free autostereoscopic displays that can be used in any display application. Real-time conversion of 2D or 3D (left/right) signals to the Ultra-D format is a key component of the Ultra-D implementation. This conversion is based on innovative depth estimation using our patented proprietary algorithms. When our business development team requested the development of an IP block for this function, we were facing a Catch-22 situation. How do we design an IP block that is suitable for IC integration without information on the semiconductors technology? Furthermore, how do we design it for multiple technologies and enable integration in multiple products with different on-chip infrastructures? In this webinar, we show how Catapult® High-Level Synthesis (HLS) development methodology has enabled this IP block development. We will also illustrate how we executed the project with a relatively small team, resulting in a complete FPGA-based validation platform. And finally, we will share some unexpected lessons and reflect on key organizational success factors.
This webinar is part 7 of the webinar series HLS for Vision and Deep Learning Hardware Accelerators.