Moving Between FPGA and ASIC with High-Level Synthesis
Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Siemen’s Catapult team about how to use HLS to accelerate your design flow.
Related resources
Optimizing HLS Code for Different FPGA Platforms
Paper examining a simple convolution filter and outlining how it can be targeted using High-Level Synthesis to different FPGA platforms.
Porting Vivado HLS Designs to Catapult HLS Platform
High-Level Synthesis (HLS) offers significant benefits when developing algorithms and intellectual property (IP).
Rapid Algorithm to HW: Using HLS for Computer Vision and Deep Learning Seminar
How HLS helps project teams rapidly & accurately explore power/performance of algorithms, quickly get to FPGA implementations to create demonstrator/prototypes & use same source RTL IP for ASIC implementation.