High-Level Verification of an AI/ML Accelerator Design
One of the fastest growing areas of hardware and software design is Artificial Intelligence/Machine Learning (AI/ML), fueled by the demand for more autonomous systems such as computer vision (CV) for self-driving vehicles, voice recognition for personal assistants and many others.
We are now seeing the emergence of customized AI/ML hardware accelerators to meet numerous, stringent, and potentially conflicting design requirements. High-Level Synthesis (HLS) can provide the needed flexibility and abstraction to efficiently and quickly realize these designs in RTL. However, when working with HLS at the C-level, many have questions about what does verification look like? Waiting to verify until you have post-HLS RTL is too late and too inefficient. This webinar demonstrates how one can achieve comprehensive verification faster at a higher level of abstraction but still apply known and trusted RTL verification techniques.
Meet the speakers
David Aerne
Verification Technologist
Dave Aerne is a Verification Technologist within the Calypto Systems Division, focusing on HLV (High-Level Verification) solutions. His particular areas of expertise are the UVM and Verification IP. Prior to joining the EDA industry, he gained over 18 years of SoC Design and Verification experience in various roles at semiconductor companies and fabless startups. Dave received a BSCompE from the University of Illinois at Urbana-Champaign and a MSCompE from National Technological University in Fort Collins, Colorado.
Jonathan Craft
HLS Verification Technologist
Jonathan Craft is an HLS Technologist at Siemens EDA focused on development of High-Level Verification (HLV) tools & methodologies. He holds a Bachelor of Science degree in Electrical Engineering from the University of Wyoming. Prior to working for Siemens, Jon held various design and verification roles performing IC and SoC development at various companies in the Denver, Colorado area.
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