High-Level Synthesis (HLS), has been adopted by leading companies to speed design time and reduce verification costs in applications such as video and image processing, 4/5G wireless, and high bandwidth advanced communications designs (i.e. optical communications processors).
But when deciding to use HLS for the first time, designers have many questions:
What does high level synthesis code look like for an algorithmic block?
How do I optimize it, and do I have enough control to get the design I want?
Will the QoR be good?
How do I verify and debug the RTL?
Should I use SystemC or C++?
This technical tutorial explores these questions and more using an iDCT for H.265 as a specific example.
What you will learn:
What High-Level Synthesis code look like for an algorithmic block
How to optimize HLS code and the level of control in the design
What the QoR will look like
How to verify and debug the RTL
Whether SystemC or C++ should be used
Who should attend:
RTL designers interesting in moving up to HLS with C/C++/System based design flow to improve productivity
RTL Design Manager/Project leaders who want to better understand what it will take and the potential benefit for the next project to move to HLS
Verification Managers who want to understand the design and verification flow using HLS