Designing ML Hardware Accelerators Using HLS Walkthrough Video Series

The following series of videos provides an introduction into designing simple ML accelerators using High-Level Synthesis (HLS). This video series is intended to be open-ended and videos will be added on more advanced topics in the near future. The example source code will become available on soon.

Enhance Your Layout Productivity Using Schematic Driven Layout (SDL)

June 10, 2021

Live Webinar


This webinar will provide an overview of how to take a schematic from S-Edit and push your netlist directly to L-Edit using Schematic Driven Layout (SDL). We will also cover productivity features in L-Edit that will allow the layout designer to quickly arrange instances and draw and verify routing connections based upon the connectivity that is transmitted using SDL.

What you will learn:
  • Pushing a schematic netlist from S-Edit to L-Edit
  • Using flylines in L-Edit
  • Manual assisted routing in L-Edit
  • Using the SDL Navigator in L-Edit
  • Checking connectivity in L-Edit on routed nets
  • Syncronization between S-Edit and L-Edit
  • ECO indications
Who should attend:
  • Analog IC layout engineers
  • Layout managers

Register now!

Meet the speakers

Photo of Karen Lujan

Karen Lujan

Product Management

Karen Lujan is a Product Line Manager for the Integrated Circuit Design Solutions Division of Siemens EDA. Karen brings a wealth of experience as a Sales Support Manager and Engineer – having served in both delivery and management roles. Karen holds a BS in Electrical Engineering and an MBA with a Technology Management focus.