Saving time and money with progressive verification

Verifying a PCB layout before sending it out to proto fab is a lot like flossing your teeth – everyone knows they should do it, but a lot of people don’t. Why should you fully verify your design after routing, even though it’s difficult?

Large, complex designs have strict requirements across multiple domains – signal and power integrity, EMC, and so on. Even when detailed routing guidelines exist, it’s often impossible to follow them exactly, and the rules get bent or broken. And then, there are just – mistakes. In complex designs, mistakes will inevitably be made, and randomly. It’s safe to say that problems will exist; it’s just a matter of whether you find them before it’s too late.

It doesn’t help that fully reviewing layouts is hard, needing expert review across multiple domains. Most reviews are based on visual inspections, and both eyes and people get tired. Manual inspection is a long, tedious process and it’s not guaranteed to find all the problems that exist.

The Progressive Verification methodology, by contrast, has the specific goal of finding problems as quickly and as easily as possible. It’s based on the observation that the time and expertise needed to perform analysis goes up non-linearly as accuracy increases. There are a lot of design problems that don’t require IBIS-AMI models and full-wave EM simulation to find. With Progressive Verification, we analyze the design in successive stages with increasing analytical detail. The bulk of the issues are found and resolved before the SI experts are brought in, so that limited SI expertise is used as cost-effectively as possible.

• We start by running electrical design rule checks during layout to look for common problems.
• Then we use Standards Compliance Analysis to look at the system-level interconnect and make sure it meets protocol requirements.
• Finally, once we’ve gotten as many problems off the table as possible, we’ll use IBIS-AMI, or vendor-based model simulation to predict how the system will perform with actual devices and settings.
• In this webinar we’ll show the results of using Progressive Verification methodology to assess a high-speed communications design that deploys a large number of 56G and 112G serial links.

What You Will Learn:

• The benefits of trading off speed vs. accuracy when verifying large systems
• How automated, expert-based rule checking can find design issues in minutes instead of hours
• The advantages of using protocol compliance analysis when verifying serial links
• Using IBIS-AMI models to establish device programming settings for system use

Who Should Attend:

• Designers who spent time waiting for someone else to model & simulate their design
• Designers and SI specialists struggling with IBIS-AMI models
• Hardware design managers looking to improve analysis coverage and reduce project schedule risk

Products Covered:

• HyperLynx DRC
• HyperLynx SI/PI
• HyperLynx Advanced Solvers