HEVC (H.265) is the latest widespread video coding standard, that doubles the coding efficiency over its predecessor AVC (H.264) for the same subjective visual quality, but typically at the cost of considerably higher computational complexity. Overcoming the complexity of HEVC and customizing its rich features for a real-time HEVC encoder implementation on hardware is not a trivial task, as hardware development has traditionally turned out to be very time-consuming. Reducing design effort, managing design complexity, increasing re-usability, ease of modification, and reduced verification time are key topics in future hardware designs that are getting more and more complex. In this webinar, Dr. Panu Sjövall will shed light on how they were able to implement their embedded real-time HEVC intra encoder on HW with Catapult HLS. Their implementation shows that HLS is able to boost the development time and still result in competitive performance and QoR over state-of-the-art hardware implementations.

What will you learn:

• Effective use of HLS for a complete HEVC intra encoder HW design
  • Using HLS for both data- and control-oriented algorithms
  • Managing the complexity
  • Verification
• Our FPGA framework to develop, verify, and deploy HLS implementations for HEVC coding

Who should attend:

• Anyone interested in HLS and FPGAs
• Anyone interested in an HEVC HW designs