Artificial Intelligence (AI) and Machine Learning (ML) are rapidly transforming many aspects of integrated circuit (IC) design. The high computational demands and evolving AI/ML workloads are dramatically impacting the architecture, VLSI implementation, and circuit design tradeoffs of hardware accelerators. To keep up with the rapid pace of change in AI/ML workloads, NVIDIA Research leverages a High-Level Synthesis (HLS) based design methodology based off SystemC and libraries such as MatchLib for maximizing code reuse and minimizing design verification effort. This methodology provides for rapid co-optimization of AI algorithms and hardware architecture and has enabled NVIDIA Research to tape out a state-of-the-art 5nm deep learning inference accelerator testchip that achieves up to 95.6 TOPS/ with per-vector scaled 4-bit quantization for Transformer neural network inference.