Energy efficiency is one of the key aspects for competitive product offering. With ever increasing demands of performance, it is imperative to design and develop silicon to meet not only performance, area goals but also energy efficiency targets. Estimation of power consumption both dynamic and leakage at early stage is key to identify areas of optimization for highly energy efficient design. At architecture phase the early power numbers are estimated using static excel based formulas or highly abstracted modelling frameworks. This approach is limited by the accuracy of the power numbers. RTL simulation tools have been traditionally used for power estimation at the pre-silicon phase, while it scales at IP level, limitation such as long runtime makes it impractical in running use cases involving multiple IPs. The ability to estimate power at RTL stage for various subsystems or at SoC level is the key to identify power bottlenecks in the entire design. In this paper we propose a novel methodology for pre-silicon power estimation and optimization. Leveraging siemens emulation technology based on Veloce and their power stream app to identify windows of interest for power analysis. Later the capabilities of Siemens PowerPro tool are used for deeper power estimation and optimization. We will present details on the correlation between the power numbers obtained through our methodology and the corresponding lab measurements.