With increasing competition and AI-driven demand, ASIC design schedules are shrinking. Given these constraints, relying solely on near sign-off power data is no longer feasible. Instead, RTL power analysis tools are being utilized early in the design process to optimize RTL for improved efficiency. As the demand for accurate early-stage power estimation grows, integrating more precise constraints into RTL power analysis becomes essential. RTL power estimation often lacks accurate physical design constraints, leading to discrepancies with gate-level power analysis. To address this, we integrate Standard Parasitic Exchange Format (SPEF) files into PowerPro RTL power analysis, significantly improving correlation with post-synthesis and post-layout estimates. SPEF provides precise resistance and capacitance values, which directly impact dynamic and leakage power. Traditional RTL estimation relies on approximate wire capacitances and switching activities, causing deviations from actual power consumption. By incorporating SPEF, we refine switching power estimation, aligning RTL-based power analysis more closely with real silicon behavior. Our methodology extracts SPEF data from a previous version of post-placed and routed design and incorporates it into PowerPro during RTL power analysis. This approach enables realistic net capacitance modeling that improves interconnect power estimation enhances overall power accuracy, including both dynamic and leakage components. We have validated this approach by comparing PowerPro-generated RTL power reports with PowerPro RTL on Gate power analysis results. Experimental results on ARM IP with different test vectors demonstrate that SPEF-based refinement significantly enhances RTL power estimation, reducing errors caused by simplified interconnect modeling. The more accurate power also makes the design metrices (e.g. clock gating efficiency) more reliable. By integrating SPEF-based constraints into PowerPro, we have enabled a predictive and reliable power analysis framework, improving energy efficiency and reducing unexpected power discrepancies in design.