Power estimation plays a crucial role in evaluating the efficiency and viability of designs. It is essential to perform power estimation throughout all stages of the design process to ensure that power consumption stays within the defined limits. As the design advances, the accuracy of power estimation improves. Achieving precise power estimation typically involves utilizing waveforms generated by simulation tools, annotated with delays from the Standard Delay Format (SDF) file. However, running simulations on a netlist with SDF annotations is computationally intensive, resulting in long runtimes. This constraint forces users to limit power estimation to small simulation windows, which increases the likelihood of errors due to incomplete or inaccurate analysis. Furthermore, obtaining accurate power estimates late in the design cycle can lead to unforeseen issues and delays. Hence, there is a pressing need for accurate power estimation early in the design process.