Samsung: Leveraging Current Profile for Power Integrity from Accurate RTL Power Analysis Early in the Design Cycle

At lower technology nodes, with ever increasing design frequencies combined with tight noise margins, the generation and management of calibration data for sophisticated power analysis has become a critical power analysis element and a bottleneck in analysis. Calibration data extracted from previous generations or as node-based average values may not be suitable for the current design, even if the design is using the same node. This discrepancy can result in inaccurate power analysis which is difficult to root-cause at the RTL stage due to lack of physical context, which is essential for reliable power integrity. Physically aware RTL power analysis enables shift-Left to obtain physical data optimized for the current design early in the design cycle. By leveraging this data, current profile can be extracted from physically aware cycle-by-cycle power analysis to find windows of interest. The qualified windows can be input into a downstream power signoff tool, enabling fast, accurate, and reliable power signoff.