LG Electronics: Video Encoder IP Design Optimization and Verification Using Catapult
As the algorithm complexity of semiconductor IP increases, design and verification times are lengthening, becoming a major factor delaying Time-To-Market (TTM). Accordingly, the semiconductor industry is focusing on securing competitiveness through PPA (Power, Performance, Area) optimization and exploring efficient development and verification methods for complex IPs. In this context, LG Electronics' SoC Center successfully designed a highly complex video encoder IP in a short period by adopting Catapult HLS. By leveraging the high-level design and verification capabilities of Catapult HLS, they were able to accelerate the design process and significantly reduce verification time. This resulted in greatly improved time and cost efficiency for IP development, and LG plans to increase the use of Catapult HLS in future development projects.
主讲嘉宾
Jonghun Yoo
Senior Researcher, SoC Center
B.S. in Computer Engineering, Gwangwoon University, 2012. M.S in Computer Engineering, Gwangwoon University, 2014. SoC R&D Center, LG Electronics, 2014 ~ Present.
- 2014 ~ 2016: Video Codec device driver development
- Present: MPEG Encoder/Decoder IP & Low Latency Video Codec IP
development
William Lee
Consultant Application Engineer
William Lee is consultant application engineer at Siemens EDA.
He is supporting Catapult HLS, which is a fast and effective RTL implementation of functions described in high level languages such as C/C++/SystemC.
He is particularly interested in HLS implementation of applications in the fields of video image processing and AI/ML.
He has also worked as an RTL design and verification support engineer, delivering QuestaSim digital logic simulator technical support and debugging, coverage closure, formal verification, and SV/UVM.
Before joining Siemens EDA in 2015, he had 6 years of experience in IP development and Soc mass production in various processes as an ASIC/SoC RTL design and verification engineer, including camera image signal processing, memory controller design, memory optimization, and low power design.
He holds a B.S and Ph.D.(ABD) degree from Hanyang University, electronics and electrical Engineering.
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