Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL / GDS) RTL lint / formal check tools cannot be run on HLS RTL (as the errors cannot be correlated to HLS source code) Onespin systemC/C++ extension DV help to overcome this challenge. This session will be presented by Siemens on behalf of Infineon Technologies AG.
主讲嘉宾简介
Vlada Kalinic
SystemC Product Specialist
Vlada Kalinic is the SystemC Product Specialist at Siemens EDA, and is involved in the evaluations with the new customers as well supporting the current portfolio of the customers to improve the current SystemC flows. Vlada has also another role, as Product Specialist of EC-FPGA in OneSpin. Vlada holds a master’s degree with honors in Electrical and Computer Engineering, Embedded Systems and Algorithms from the University of Novi Sad (Serbia). Prior to Mentor/Siemens, Vlada worked with OneSpin for 5+ years and was involved in various successful evaluations with SystemC and EC-FPGA customers.
相关资源
2030 年的船舶行业：引领数字化船队
行业顶级分析师阐述数字化双胞胎和智能技术的使用怎样创造出可用于优化船队运营的见解。
2030 年的船舶行业：船舶数字化劳动力
数字化正推动着船舶行业转型。了解如何使用虚拟和增强现实技术改善船舶运营、船员培训并实现远程协助。
数字化双胞胎在海事领域中的应用
航运业正经历着波涛汹涌般的震荡。经济不稳定持续影响着饱和的航运市场，船东和运营商需要通过提高运营可用性和降低运营成本来实现利润最大化。与此同时，信息和通信技术 (ICT) 的兴起使数据采集、交换和分析发展到了前所未有的水平，为航运公司和船舶制造商打开了新局面。那么，船舶行业如何利用这种大量新增的可用数据呢？