Visualizer Debug Environment automates debugging for the digital design and verification of today's complex SoCs and FPGAs. Find bugs faster in the Visualizer Debug Environment, a high-performance, high-capacity debugger. Tightly integrated with both Questa Simulation and Veloce Emulation, it provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog, VHDL, SystemC and C/C++. In addition to being very intuitive and easy to use in either interactive debug or post simulation mode, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.
Product Engineer
Rich Edelman is a Product Engineer at Siemens EDA for the Visualizer Debug Environment. He is a verification technologist helping customers adopt successful techniques for UVM and class based testbenches. Rich previous work includes register verification, SystemVerilog DPI development and transaction recording interfaces for Questa. Rich graduated from Washington University in St. Louis with a bachelor's degree in Computer Science, a bachelor's degree in electrical engineering and a master's degree in computer science.