High-Level Verification of an AI/ML Accelerator Design

One of the fastest growing areas of hardware and software design is Artificial Intelligence/Machine Learning (AI/ML), fueled by the demand for more autonomous systems such as computer vision (CV) for self-driving vehicles, voice recognition for personal assistants and many others.  

We are now seeing the emergence of customized AI/ML hardware accelerators to meet numerous, stringent, and potentially conflicting design requirements. High-Level Synthesis (HLS) can provide the needed flexibility and abstraction to efficiently and quickly realize these designs in RTL. However, when working with HLS at the C-level, many have questions about what does verification look like? Waiting to verify until you have post-HLS RTL is too late and too inefficient. This webinar demonstrates how one can achieve comprehensive verification faster at a higher level of abstraction but still apply known and trusted RTL verification techniques.