Design Methodology for Building Power Efficient RTL Seminar

The growth of semiconductor industry hinges on the fact that with every new generation, chips would have higher performance and consume less power. However, we are witnessing that scaling through Moore’s law does not automatically translate to efficiency gains in terms of energy anymore. That’s why regardless of the application area - networking, computation, or storage - power and energy consumption can make the difference between a differentiated product and a product that does not meet customer needs. In the 2020 survey by Wilson Research, power is now the #3 reason for design re-spins.

That brings power at the front and center in silicon design process. It is obvious that we cannot wait until the very end of their design cycle to try to fix power problems and it needs to be considered during the architecture and design phase. We need an effective hardware design methodology to deliver lowest power RTL IP and/or designs.

This seminar will highlight how power and energy metrics and optimization can predictably deliver the best quality RTL optimized for power. It will feature a combination of technical sessions and user case studies delivered by people who have adopted those best practices to build successful products.

Sessions

Seminar Introduction and Customer Case Studies  
This session will provide an overview of the seminar and key learning objectives. It will introduce a design flow - adopted by companies from ARM to Cisco – to build energy efficient RTL IP. The session will go over the value of thinking about power early in the design cycle.
Speaker: Anoop Saha

30 min - Arm: Decarbonizing Compute Through Energy-Efficient IP Design  
The climate crisis is the greatest challenge facing humanity today. As demand for cloud services and digital technologies grows, reducing their environmental impact is critical. Technology roadmaps must make decarbonization a priority. ​ Hardware design has a key role to play. From increasing performance per watt and eliminating unnecessary compute to unlocking further optimizations, energy-efficient IP can significantly impact technology’s global carbon footprint. This presentation highlights the challenges – both real and perceived – to decarbonization and considers approaches for achieving energy efficiency in hardware design.
Speaker: Arm Inc.: Pierre-Alexandre Bou-Ach

30 min - Fast-tracking low-power design with an early power methodology 
Low-power is a subject of great attention and rightly so. Power can lead to design re-spins and competitive disadvantage for products. A low-power methodology from early RTL design to RTL sign-off can simplify design-for-low-power and also uncover downstream power sign-off issues, avoiding costly late-stage changes. Learn how a low-power methodology can be established that treats power as a first-class citizen and ensures the development of energy efficient IPs that are free of potential power issues which can cause chip failures.
Speaker: Qazi Ahmed

Building Power Efficient Cisco Network Switches Through PowerPro Guidance, Early Tracking and Optimization 
Building on their success in reducing power consumption with PowerPro via a clock gating efficiency gain of 10-20% with vectorless optimization, Cisco's Udupi Harisharan will discuss the usefulness of other tool features to guide designers in making effective clock gating decisions and the feeding back of key power metrics to the design team during RTL development.
Speaker: Cisco: Udupi Harisharan

Fast and Accurate Power Analysis Using PowerPro – From IP to System 
With increasing design complexities targeting ever-shrinking geometries, the Power Analysis tools are posed with a challenge of estimating power for these massively large designs with billions of gates with billions of cycles to estimate power under real workload scenarios. Challenge is that it must be accurate and has to be done quickly with fewer iterations. In this session, we are presenting how PowerPro’s enhanced Power Analysis solution and its integration with Veloce is helping user estimate the Power across the project development cycle from IP to System level.
Speaker: Mohammed Fahad and Mahmud Ullah