VIP solutions for Protocol and Memory Verification

March 11, 2021 08:00 AM US/Pacific


The silicon industry’s leading IP, FPGA, and IC design/verification teams are using Siemens EDA Verification IP solutions today to solve the verification of complex Protocol and Memory Interfaces. In this 30 minute session, we'll provide an introduction to the solutions available from Siemens EDA, a description of the key attributes of the Verification IP and Memory Model products, and a high level summary of how they can be used to bring quality and time-to-market value to your project.

What You Will Learn:

  • The challenges of verifying today’s advanced interface and memory protocols
  • The broad portfolio of Siemens EDA Verification IP solutions available today
  • The architecture, features, and rigor you should expect from a good Verification IP solution

Who Should Attend:

  • Design & Verification Engineers & Managers and those interested in Protocol or Memory Interface verification

Meet the speakers

Photo of Gordon Allan
Siemens EDA

Gordon Allan

Verification IP Product Manager

Gordon Allan is Product Manager for Verification IP at Siemens EDA. Gordon was one of the authors of Accellera UVM, and he published the online UVM Cookbook on our Verification Academy site where it is appreciated by over 40,000 engineers today. Prior to joining the EDA industry he gained over 18 years of Design/Verification experience leading & developing SoC and complex protocol IP/VIP projects in several semiconductor companies, fabless startups, EDA and system houses. Gordon is based in Silicon Valley.
Photo of Tom Fitzpatrick
Siemens EDA

Tom Fitzpatrick

Strategic Verification Architect

Tom is a Strategic Verification Architect at Siemens Digital Industries Software (Siemens EDA) where he works on developing advanced verification methodologies and educating users and partners on their adoption. He has been a significant contributor to several industry standards, both in Accellera and IEEE, including Verilog 1364, SystemVerilog 1800, UVM 1800.2 and is a founding member and current Vice Chair of the Portable Stimulus Working Group. He is also the 2019 recipient of the Accellera Technical Excellence Award. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification, Portable Stimulus and other functional verification topics and has produced some of the most popular and successful video training courses on Mentor's Verification Academy website. Tom holds Master’s and Bachelor’s degrees in EE/CS from MIT, is an avid golfer and a huge Boston Red Sox and New England Patriots fan and has been married to his wife, Dee, for 25 years.


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