Microsoft: Untimed C++ HLS — Level-Up
C++ HLS offers numerous intrinsic advantages yet also presents certain challenges in hardware design. This presentation discusses some of the hurdles in C++ hardware design we address through our in-house developed libraries to level up hardware simulation, debug, and integration with RTL designs.
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Robert Havlik
Principal Design Engineer
Robert Havlik holds a Master's Degree from the University of Colorado, Boulder in Electrical and Computer Engineering. He has extensive experience in both FPGA and ASIC development from Analog and Physical Design to RTL, High Level Synthesis, and Verification with a focus on hardware acceleration. He has worked on variety of projects leveraging HLS technologies, targeting both ASICs and FPGAs across domains of image processing, computer graphics, AI, compression, networking, and storage.