Verilog Basics for SystemVerilog Constrained Random Verification
Learn how to parse Verilog expressions.
Constrained Random Verification (CRV) addresses the time-consuming task of writing individual directed tests for complex systems. We sometimes say that CRV automates writing tests for quickly producing the test cases you can think of or hitting the corner cases you didn’t. But the reality is, like with any computer programming language, your code executes exactly the way it is written, and has no concern for what you were thinking. In particular when coding constraints, this manifests as results that satisfy the constraints, but may not match what you intend. Crashes or conflicting constraint failures are usually easier to resolve because of their abrupt termination. However, without an abrupt termination, you may not notice anything wrong with the results until much later in the process; perhaps after you check your functional coverage reports.
This webinar looks at two of the most common issues when constraint solver results do not match your intent: 1) not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra, and 2) not understanding the affect probability has on choosing solution values.
What You Will Learn:
- How to parse Verilog expressions
- Why expressions in verification must have the same semantics as synthesis
- How probabilities and statistics affect constraint results
Meet the speaker
Dave Rich
Product Engineering
Dave Rich is member of the Flows and Methodology Product Engineering team for Siemens EDA. He is chartered with streamlining our testbench flows as they interact with a number of our products, especially around the Questa Simulation platform. Dave brings over three decades of design and verification experience to bear on developing advanced verification methodologies. He has been actively involved in the standardization of SystemVerilog, via Accellera and then the IEEE, where he has served as co- chair of the Technical Champions committee in the SystemVerilog IEEE 1800 Working Group. At Mentor Graphics, Dave was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM). Prior to that, Dave worked on early simulation and synthesis technologies at a variety of EDA companies.