Verification Signoff of HLS C++/SystemC Designs
Adoption of HLS (High-Level Synthesis) continues to grow yet there is also a need for associated HLV (High-Level Verification) methodologies. The motivation for this need is verification at the C++ level (versus RTL) has been shown to reduce overall verification costs by as much as 80%. This webinar introduces Catapult “HLS-Aware” C++/SystemC verification tools and flows that will efficiently help find and eliminate bugs early, ensure C→RTL correctness and rapidly close coverage on both the C++ design source and the HLS-generated RTL.
What You Will Learn
- HLV tools and flows thus providing opportunity for verification signoff of HLS C++ design source
- Examples include:
- Using lint and formal tools to ensure correctness of C++ design source prior to synthesis
- Using portable stimulus to target efficient constrained random stimulus for C++ test benches
- Achieving both code and functional coverage goals on the HLS C++ design source
- Use of SLEC formal methods to confirm equivalence between the generated RTL and the C++ design source
Who Should View
- Project leads curious to learn how HLV can improve productivity and reduce schedule uncertainty
- Teams considering HLS and curios to learn about the corresponding HLV methodologies
- Design and Verification teams currently using HLS yet curious to learn what's new on the HLV side
Meet the speaker
David Aerne
Verification Technologist
Dave Aerne is a Verification Technologist within the Calypto Systems Division, focusing on HLV (High-Level Verification) solutions. His particular areas of expertise are the UVM and Verification IP. Prior to joining the EDA industry, he gained over 18 years of SoC Design and Verification experience in various roles at semiconductor companies and fabless startups. Dave received a BSCompE from the University of Illinois at Urbana-Champaign and a MSCompE from National Technological University in Fort Collins, Colorado.