On-Demand Webinar

UVVM – the main benefits of the world’s #1 VHDL verification methodology


Are you developing FPGAs or ASICs using VHDL as your design language?

If so – you should most probably also use VHDL as your verification language - as that will result in a better quality and faster development for a huge majority of projects. But this only applies if you use the right verification methodology. The difference between the best methodology and a mediocre methodology could easily be a factor of 2 or 3 for development time - and even worse for quality,

The right methodology is one that allows the best possible testbench architecture, simplest possible test sequencers and the most efficient reuse both inside and between projects. UVVM – the Universal VHDL Verification Methodology is an open-source methodology and library that has grown faster than any other verification methodology over the last few years - just because it has had this as the main target all the way. This has resulted in the best possible overview, readability, maintainability, extensibility and reuse.

In this webinar, we will give a brief introduction to UVVM and the main benefits of this methodology, and also explain how this is different from similar methodologies around.

What you will learn:

  • Modern state of the art verification methodology in general

  • The basics of UVVM for simple test benches

  • The basics of UVVM for advanced test benches

  • The main benefits of UVVM

  • Why UVVM is better

Who should view:

  • VHDL designers

  • Designers and verification engineers who want to use VHDL for verification

  • Technical managers and Project managers who wants to get an overview of structured VHDL verification

  • Anyone interested in evaluating UVVM for their next project