On-Demand Webinar

UVM Coding Guidelines:

Tips & tricks you probably didn’t know

Estimated Watching Time: 21 minutes

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Configuration tip: Make your DUT topology match the testbench and config

Chris Spear, Principle Instructor presents coding guidelines for UVM, the Universal Verification Methodology. He recommends how to create testbench transactions and component classes that are easily debugged and reused. Additional rules are shown for SystemVerilog code to prevent common bugs. These strategies are based on decades of experience with functional verification in Verilog, SystemVerilog, and verification methodologies including UVM, OVM, VMM, and more.

What you will learn:

  • High performance method to distribute configuration information throughout a testbench

  • A simple Object Oriented Programming method that is more robust and easier to use than the UVM configuration database (uvm_config_db)

  • Do’s and don’ts on creating UVM sequence item classes to describe your transactions

  • A simple approach to starting sequences of transactions, and sharing configuration information

  • Creating methods to provide a high-level interface to sequences

  • Tradeoffs between the uvm_do macros and their atomic operations

  • Improving simulation performance with phase objection alternatives

  • The best way to perform and check SystemVerilog randomization

  • A common Verilog expression gotcha that trips even experienced coders

Meet the speaker

Siemens EDA

Chris Spear

Functional Verification Principal Instructor

Chris brings over twenty five years of EDA expertise to Siemens EDA customers and is currently a Functional Verification Principal Instructor with Mentor Learning Services. Holding a degree in electrical engineering from Cornell University, Chris has developed deep roots in the EDA industry, including as a Principal Application Consultant with Synopsys. Chris is also an industry author, writing the 2012 best-selling “SystemVerilog for Verification” and developing the IEEE standard for random seeding and File I/O PLI package that is part of SystemVerilog. Having taught thousands of engineers around the world, Chris is driven by a passion for learning new techniques and then helping others learn best practices for hardware verification. Outside of work, you may see Chris bicycling over 10,000-foot mountain passes.