Using Calibre for High-Density Advanced IC Packaging (HDAP) Verification - Part 1

Every chip must be packaged, and High-Density Advanced Packaging (HDAP) is a rapidly expanding technology that leverages heterogeneous multi-chip integration to deliver the performance, functional density and cost targets that multiple market segments are demanding. Siemens Xpedition and Calibre technologies provide a proven path to HDAP design, comprehensive verification and foundry/OSAT signoff.

Watch this on-demand webinar to learn why many of the leading fabless semiconductor companies choose to verify their HDAP assemblies with Calibre.

What is high-density advanced IC packaging (HDAP) and what are the verification challenges?

Siemens created the term high-density advanced packaging (HDAP) to categorize advanced packaging technologies that we see as disruptive to traditional tools and methodologies and generally need a new approach to the planning, design, verification and signoff methodology.

HDAP demands extensive verification at multiple levels, not limited to verification of the individual die and substrates but also at the complete assembly level. This verification includes layout versus schematics (LVS) to check the system-level connectivity of the completed substrates against the virtual model, which has the golden netlist. Layout versus layout (LVL) allows for alignment checking of die, substrates and other component interfaces, possibly compromised by the fabrication process.

High-density advanced IC packaging types

There are four categories of high-density advanced packaging types:

• Fan-out wafer level packaging (FOWLP)
• High-density flip-chip
• System-in-package (SiP)/modules
• 2.5D/3D heterogeneous integration

See a demonstration of what a FOWLP HDAP design looks like inside Siemens design tools.

Advanced IC packaging for “More than Moore”

Monolithic SoC design is no longer the path for achieving the functionality many applications demand. The emerging alternative trend is to disaggregate a monolithic device into a collection of node-optimized heterogeneous or homogeneous chips or chiplets. Chipmakers interconnect these chiplets on a high-performance interposer as part of an advanced IC package typically known as 2.5D.

Advanced 2D and 3D packaging technologies allow semiconductor designers to flexibly combine smaller process-optimized chiplets to meet the demand of a wide range of applications.