Trouble: Three CDC Glitches That Only a Netlist Will See

May 18, 2021 08:00 AM US/Pacific

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As the industry increases investments in automotive and safety-critical design, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals reduce reliability and lead to potential silicon failures. An increasing number of companies deploy CDC verification at both the RTL and the gate-level. To identify potential glitches on CDC paths at the gate-level, we use Signoff CDC, a tool that utilizes structural CDC analysis, expression analysis, and formal methods to prune and prove real glitches in the design.

This session will help you lower risks, development schedules and costs by identifying netlist CDC issues that are never caught with normal RTL CDC runs.

What You Will Learn:

  • Why you need to be running gate-level CDC verification
  • How to identify and fix the “three witches” that cause glitches and break CDC paths
  • How to add netlist CDC to your CDC flow

 Who Should Attend:

  • Design & Verification Engineers & Managers

Product Covered:

  • Questa Signoff CDC

Meet the speakers

Photo of Ping Yeung
Siemens EDA

Ping Yeung

Principal Engineer

Ping Yeung, Ph.D. is the Principal Engineer in Siemens EDA. He has over 20 years of application, marketing, and product development experience in the EDA industry, including positions at 0-In, Synopsys, and Mentor. He holds 7 patents in the CDC and formal verification areas.
Photo of Kurt Takara
Siemens EDA

Kurt Takara

Lead Product Engineer

Kurt Takara is the Lead Product Engineer for Questa CDC+RDC at Siemens EDA, and has over 20 years of experience in engineering design and verification, technical marketing and engineering services. Takara has held engineering, marketing, consulting services and project management roles in electronics and EDA companies such as 0-In Design Automation, Synopsys, Ikos Systems, Raytheon and Magnavox. He holds a BSEE from Purdue University and an MBA from Santa Clara University.
Photo of Chris Giles
Siemens EDA

Chris Giles

Design Solutions Product Manager

Chris is a member of the DVT Product Marketing team, managing the Design Solutions product line, including the CDC+RDC product lines as well as the HDL Designer Series. Chris comes to Siemens EDA from the user community, with decades of experience in IP and ASIC/SoC/FPGA R&D and management, with products deployed in consumer, military, compute and storage markets and at companies such as Hewlett Packard Enterprise, Honeywell, Seagate, Micron, NEC and LSI Logic. The author of 18 patents in areas such as hardware virtualization, security, processor architecture, synchronization schemes, and hardware prototyping, Chris received an MSEE from Stanford University in California and a BSEE from Rice University in Texas.


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