Tackling the Challenges of High-Performance Low-Power SerDes Design and Verification

Learn about a case study of a low-power 14Gb/s transceiver using a partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery. We will describe circuit architecture, highlight the circuit verification challenges, and share results of our use of the Analog FastSPICE (AFS) Platform to address those challenges at the block level and at the full-circuit level. AFS enabled us to have a successful 65nm tape out of the design, achieving a power efficiency of 2.8mW/Gb/s and BER <10-12, while operating at 14Gb/s with 12dB channel loss.